The present invention generally relates to the field of chemical mechanical polishing. More particularly, the present invention is directed to a chemical mechanical polishing method for reducing slurry reflux.
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting and dielectric materials are deposited onto and etched from a surface of a semiconductor wafer. Thin layers of conducting, semiconducting and dielectric materials may be deposited by a number of deposition techniques. Common deposition techniques in modern wafer processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) and electrochemical plating. Common etching techniques include wet and dry isotropic and anisotropic etching, among others.
As layers of materials are sequentially deposited and etched, the uppermost surface of the wafer becomes non-planar. Because subsequent semiconductor processing (e.g., photolithography) requires the wafer to have a flat surface, the wafer needs to be planarized. Planarization is useful for removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize workpieces, such as semiconductor wafers. In conventional CMP utilizing a dual-axis rotary polisher, a wafer carrier, or polishing head, is mounted on a carrier assembly. The polishing head holds the wafer and positions the wafer in contact with a polishing layer of a polishing pad within the CMP polisher. The polishing pad has a diameter greater than twice the diameter of the wafer being planarized. During polishing, each of the polishing pad and wafer is rotated about its concentric center while the wafer is engaged with the polishing layer. The rotational axis of the wafer is offset relative to the rotational axis of the polishing pad by a distance greater than the radius of the wafer such that the rotation of the pad sweeps out a ring-shaped “wafer track” on the polishing layer of the pad. The width of the wafer track is equal to the diameter of the wafer when the only movement of the wafer is rotational. However, in some dual-axis CMP polishers, the wafer is also oscillated in a plane perpendicular to its rotational axis. In this case, the width of the wafer track is wider than the diameter of the wafer by an amount that accounts for the displacement due to the oscillation. The carrier assembly provides a controllable pressure between the wafer and polishing pad. During polishing, a slurry, or other polishing medium, is flowed onto the polishing layer and into the gap between the wafer and polishing layer. The wafer surface is polished and made planar by chemical and mechanical action of the polishing layer and slurry on the surface.
The interaction among polishing layers, polishing slurries and wafer surfaces during CMP is being increasingly studied in an effort to optimize polishing pad designs. Most of the polishing pad developments over the years have been empirical in nature. In addition, much of the design of polishing layers has focused primarily on providing these layers with various patterns and configurations of voids and grooves that are claimed to enhance slurry utilization and polishing uniformity. Over the years, quite a few different groove and void patterns and configurations have been implemented. Prior art groove patterns include radial, concentric circular, Cartesian grid and spiral, among others. Prior art groove configurations include configurations wherein the depth of all the grooves are uniform among all grooves and configurations wherein the depth of the grooves varies from one groove to another.
Some CMP pad designers have considered the effect of the rotation of the polishing pad on polish uniformity, e.g., observing that regions of the wafer more distal from the rotational axis of the polishing pad are swept by a greater area of the polishing surface. For example, in U.S. Pat. No. 5,020,283 to Tuttle, Tuttle discloses that in order to achieve a uniform removal rate relative to the distance from a polished region of the wafer to the rotational axis of the polishing pad, it is desirable to increase the void ratio within the polishing layer with increasing radial distance from the axis of pad rotation. In addition to considering the effect of pad rotation on the polish uniformity, it is generally recognized that in the context of dual-axis CMP polishers, described generally above, that if no polishing slurry were present, optimal polish uniformity is achieved when the rotational speeds of the pad and wafer are equal to each other (i.e., synchronous). However, it has been observed that once polishing slurry is introduced into a synchronous dual-axis polisher, polishing uniformity often becomes diminished.
Although the rotation of the polishing pad has been considered in designing prior art CMP processes and the benefits of synchronous rotation in the absence of polishing slurry are known, it appears that the effects of relative rotational speeds of the polishing pad and wafer in the presence of polishing slurry have not been fully considered in optimizing CMP using dual-axis polishers. In addition, similar principles do not appear to have been considered in connection with other types of polishers, such as belt-type polishers. Accordingly, there is a need for a CMP method that optimizes polishing uniformity based upon the relative speeds of the polishing pad and wafer. There is also a need for a CMP method that reduces the defectivity, i.e., the occurrence of defects such as macro-scratches, of the polished surface.